`timescale 1ns / 1ps

module axil_dpi_top_module;

    localparam DATA_WIDTH = 32;
    localparam DPI_ADDR_WIDTH = 32;
    localparam AXIL_ADDR_WIDTH = 16;

    logic clk;
    logic rst;

    // from dpi to axil
    logic write_en; 
    logic read_en;
    logic req_valid;

    logic [DPI_ADDR_WIDTH-1:0] req_addr;
    logic [DATA_WIDTH-1:0] req_data;

    logic ready;

    // from axil to dpi
    logic busy;

    logic resp_valid;
    logic [AXIL_ADDR_WIDTH-1:0] resp_addr;
    logic [DATA_WIDTH-1:0] resp_data;

    // addr width trans: 32bits <-> 16bits
    logic [AXIL_ADDR_WIDTH-1:0] dpi_to_axil_req_addr;
    logic [DPI_ADDR_WIDTH-1:0]  axil_to_dpi_resp_addr;

    assign dpi_to_axil_req_addr = req_addr[15:0];
    assign axil_to_dpi_resp_addr = {16'b0,resp_addr};

    dpi_interface dpi_inter0 (
        .clk(clk),
        .rst(rst),
        .write_en(write_en),
        .read_en(read_en),
        .req_valid(req_valid),
        .busy(busy),
        .ready(ready),
        .req_addr(req_addr),
        .req_data(req_data),
        .resp_valid(resp_valid),
        .resp_addr(axil_to_dpi_resp_addr),
        .resp_data(resp_data)
    );

    axil_interface axi_inter0(
        .clk(clk),
        .rst(rst),
        .write_en(write_en),
        .read_en(read_en),
        .req_valid(req_valid),
        .ready(ready),
        .busy(busy),
        .resp_valid(resp_valid),
        .req_addr(dpi_to_axil_req_addr),
        .req_data(req_data),

        .resp_addr(resp_addr),
        .resp_data(resp_data)
    );

    always begin
        #5 clk = ~clk;
    end

    initial begin
        clk = 0;
        rst = 1;
        # 10
        rst = 0;
        # 10
        ;
    end

endmodule
